As next-generation materials for power semiconductor devices, silicon carbide (hereinafter, also referred to as SiC) is expected. SiC has superior physical properties to Si; specifically, the band gap is three times higher, the breakdown field strength is about ten times higher, and the thermal conductivity is about three times higher. By utilizing such properties, an ultra-low-power-loss and high-temperature operable power semiconductor device can be implemented.
There are a variety of high breakdown voltage semiconductor devices using such SiC properties. As one of such devices, a Double Implantation MOSFET (hereinafter, referred to as DIMOSFET) is known in which p-wells and source regions are formed by ion implantation.
A DIMOSFET uses a planar process in which channels can be formed with higher accuracy by an ion implantation process, and thus fabrication thereof is easy. In addition, since gate drive is controlled by voltage, the power of a drive circuit can be reduced and thus a DIMOSFET is an excellent device suitable also for parallel operation.
However, in a SiC DIMOSFET, the electric field applied to an upper portion of a portion sandwiched between facing p-wells (hereinafter, referred to as JFET region) is high because of its structure. Hence, there is a problem that device breakdown occurs in a gate insulating film formed on a surface of a JFET portion.